Synchronous digital circuits can be subject to set-up timing errors. A set-up timing error occurs when the circuit does not achieve a specific well-defined data state—either high or low—before the subsequent rising edge of the clock signal. Setup timing errors can occur due to several reasons, such as ageing, voltage scaling, frequency scaling, etc.
Set-up timing errors can be detected using, for example, double sampling flip-flops. Once an error is detected, it can generally be masked, for instance by “borrowing” time from a subsequent stage, in particular the next downstream pipeline stage, which is typically a further logic block. The error, thus masked, propagates through the logic without causing failures. However, in some architectures, this may not be possible, in particular in the presence of a hard macro. As will be described in more detail hereinbelow, in this disclosure, a hard macro, also known as hard core of hard IP, refers to a circuit element or block, at the input of which timing errors either cannot be tolerated, or are undetectable.